The present invention relates to a solid-state imaging device and an electronic apparatus.
An electronic apparatus, such as a digital video camera or a digital still camera, includes a solid-state imaging device. In the solid-state imaging device, an imaging region in which a plurality of pixels are arranged in a matrix includes an image sensor chip on the surface of a semiconductor substrate. For example, the imaging region includes a CCD (Charge Coupled Device) or CMOS (Complementary Metal Oxide Semiconductor) image sensor chip.
In the image sensor chip, a photoelectric conversion section is provided in each of a plurality of pixels. The photoelectric conversion section is, for example, a photodiode, and receives light input through an external optical system in a light receiving surface and carries out photoelectric conversion to generate signal charges.
In the solid-state imaging device, signal processing is performed for an output signal which is output from the image sensor chip.
On the other hand, there is demand for reducing the size of the solid-state imaging device.
For this reason, in the solid-state imaging device, a technique has been proposed in which both the image sensor chip and the signal processing chip which performs signal processing for an output signal are mounted in a single multilayer wiring package (Japanese Patent No. 3417225 (FIG. 1 and the like)).
In addition, for explanatory purposes, the inventors of the present invention have included the following discussion to explain issues that they have recognized and have overcome with the present invention. In this regard, FIGS. 24A to 24C are diagrams schematically showing a solid-state imaging device.
FIG. 24A shows an upper surface. FIG. 24B shows a cross-section taken along the line X1-X2 of FIG. 24A. FIG. 24C shows a cross-section taken along the line Y1-Y2 of FIG. 24A.
As shown in FIGS. 24A to 24C, the solid-state imaging device includes an image sensor chip 100, a signal processing chip 200, and a multilayer wiring ceramic package 300Z.
The image sensor chip 100 is, for example, a CCD. As shown in FIG. 24A, the image sensor chip 100 carries out imaging in an imaging region PA. In the imaging region PA, a plurality of pixels (not shown) are arranged in a matrix, and receive incident light as a subject image and generate signal charges. In the image sensor chip 100, an output circuit is provided in a peripheral region SA around the imaging region PA, and outputs the signal charges transferred from the imaging region PA as an output signal.
The signal processing chip 200 is, for example, an analog front end (AFE) or an analog-to-digital converter (ADC), and performs signal processing for an output signal from the image sensor chip 100.
As shown in FIGS. 24A to 24C, in the multilayer wiring ceramic package 300Z, both the image sensor chip 100 and the signal processing chip 200 are mounted.
Specifically, as shown in FIGS. 24B and 24C, the image sensor chip 100 is provided on the upper surface of the multilayer wiring ceramic package 300Z. An accommodating space SP1 which is depressed in a concave shape is provided in the upper surface of the multilayer wiring ceramic package 300Z, and the image sensor chip 100 is accommodated in the accommodating space SP1. The image sensor chip 100 is mounted with a die bond material 710 on a bottom surface S12 of the accommodating space SP1. Surface S12 may serve as a die attachment surface. As shown in FIG. 24B, a step is provided in the accommodating space SP1, and wires 810 are provided between a surface S11 of the step and the surface of the image sensor chip 100 provided on the bottom surface S12 to electrically connect the surface S11 of the step and the surface of the image sensor chip 100.
As shown in FIGS. 24B and 24C, a glass plate 400 is bonded to the upper surface of the multilayer wiring ceramic package 300Z by a seal material 740 so as to seal the accommodating space SP1. Discrete components 500 are provided around the glass plate 400 on the upper surface of the multilayer wiring ceramic package 300Z.
On the other hand, as shown in FIGS. 24B and 24C, the signal processing chip 200 is mounted on the lower surface of the multilayer wiring ceramic package 300Z. An accommodating space SP2 which is depressed in a concave shape is provided in the lower surface of the multilayer wiring ceramic package 300Z, and the signal processing chip 200 is accommodated in the accommodating space SP2. The signal processing chip 200 is mounted with a die bond material 720 on a bottom surface S22 of the accommodating space SP2. Surface S22 may serve as a die attachment surface. As shown in FIGS. 24B and 24C, a step is provided in the accommodating space SP2, and wires 820 are provided between a surface S21 of the step and the surface of the signal processing chip 200 provided on the bottom surface S22 to electrically connect the surface S21 of the step and the surface of the signal processing chip 200.
As shown in FIGS. 24B and 24C, a filled layer 600 is provided in the lower surface of the multilayer wiring ceramic package 300Z so as to fill the accommodating space SP2.
As shown in FIG. 24A, external leads 310 are provided in the upper and lower end portions of the multilayer wiring ceramic package 300Z.
In the solid-state imaging device, the image sensor chip 100 is configured such that there is little power consumption in the imaging region PA, and most of power consumption occurs in the peripheral region SA where a peripheral circuit, such as an output circuit having a source follower circuit, is provided. In the solid-state imaging device, the image sensor chip 100 has power consumption higher than the signal processing chip 200.
For this reason, in the solid-state imaging device, the signal processing chip 200 becomes a heat source, and heat of the signal processing chip 200 is transmitted to the imaging region PA of the image sensor chip 100, causing a rise in temperature of the imaging region PA. As a result, the dark current characteristic may be significantly deteriorated.
FIG. 25 is a diagram showing the relationship between environmental temperature and dark current in a solid-state imaging device.
As shown in FIG. 25, it can be understood that, with a rise in temperature of several ° C. to 10° C., the occurrence of dark current is deteriorated about 1.5 to 3 times.
With the occurrence of dark current, the image quality of captured images may be degraded.
Hence, in the solid-state imaging device, it is difficult to realize reduction in size and improvement in the image quality of captured images.